The present invention relates to a standard cell, a semiconductor device having standard cells, and a method for laying out and wiring the standard cell.
Such a semiconductor device as SOC (System On Chip) is designed using standard cells. The following Patent Documents 1 to 7 each disclose a technique for reducing the area of a chip in a semiconductor device which is designed using standard cells.
Japanese Unexamined Patent Publication No. 2001-15602 (Patent Document 1) discloses a standard cell including a VDD terminal formed by a p-type diffusion layer, a VSS terminal formed by an n-type diffusion layer, and input and output terminals formed by a metal layer, the diffusion layers and the metal layer being coupled together through contact holes.
Japanese Unexamined Patent Publication No. 2001-189427 (Patent Document 2) discloses a standard cell wherein a GND wire is disposed in a first metal layer and a VDD trunk is disposed in a second metal layer.
Japanese Unexamined Patent Publication No. 2005-236107 (Patent Document 3) discloses a standard cell including a basic power supply metal layer disposed above a circuit, a transistor element layer formed on a circuit board under the basic power supply metal layer, and an internal wiring layer for supplying a supply voltage from the basic power supply metal layer to the transistor element layer.
Japanese Unexamined Patent Publication No. Hei 8 (1996)-222640 (Patent Document 4) discloses a standard cell including an n-type high density region provided on an upper side of an n-type substrate and coupled to a conductor for power supply and a p-type high density region provided on a lower side of a p-type well and coupled to a conductor for grounding, the n- and p-type high density regions being continuous with each other between the standard cell and a standard cell adjacent thereto in a cell row direction.
Japanese Unexamined Patent Publication No. 2008-4790 (Patent Document 5) discloses a standard cell including an active region provided between a VDD trunk and a GND trunk, a plurality of transistors formed in the active region, and coupling portions extended from the active region up to below the VDD trunk and the GND trunk, the coupling portions being coupled to the VDD trunk and the GND trunk respectively.
Japanese Unexamined Patent Publication No. Hei 7 (1995)-249747 (Patent Document 6) discloses a standard cell wherein an n-type channel transistor and a p-type channel transistor are arranged in the channel width direction between a drain electrode region and an earth electrode region.
Japanese Unexamined Patent Publication No. 2009-158728 (Patent Document 7) discloses a standard cell including a semiconductor substrate, a contact region formed on the surface of the semiconductor substrate, an interlayer dielectric film formed on the semiconductor substrate, an open trench formed within the interlayer dielectric film and extended linearly up to the contact region, and a conductive layer buried within the open trench and coupled electrically to the contact region.